0 Happy New Year!

Cheers to a New Year and another chance for us to get it right.

Oprah Winfrey

0 Merry X- Mas

Hi friends...

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0 SEMESTER VIII

MG1352 – TOTAL QUALITY MANAGEMENT

(Common to Biomedical, CSE, ECE and IT)

UNIT I INTRODUCTION 9

Definition of quality – Dimensions of quality – Quality planning – Quality costs – Analysis techniques for quality costs – Basic concepts of Total Quality Management – Historical review – Principles of TQM – Leadership – Concepts – Role of senior management – Quality Council – Quality statements – Strategic planning – Deming philosophy – Barriers to TQM Implementation.

UNIT II TQM PRINCIPLES 9

Customer satisfaction – Customer perception of quality – Customer complaints – Service quality –Customer retention – Employee involvement – Motivation, empowerment, teams, recognition and reward – Performance appraisal – Benefits – Continuous process improvement – Juran trilogy – PDSA cycle – 5S – Kaizen – Supplier partnership – Partnering – Sourcing – Supplier selection – Supplier rating – Relationship development – Performance measures – Basic concepts – Strategy – Performance measure.

UNIT III STATISTICAL PROCESS CONTROL (SPC) 9

The seven tools of quality – Statistical fundamentals – Measures of central tendency and dispersion – Population and sample – Normal curve – Control charts for variables and attributes – Process capability – Concept of six sigma – New seven management tools.

UNIT IV TQM TOOLS 9

Benchmarking – Reasons to benchmark – Benchmarking process – Quality Function Deployment (QFD) – House of quality – QFD process – Benefits – Taguchi quality loss function – Total Productive Maintenance (TPM) – Concept – Improvement needs – FMEA – Stages of FMEA.

UNIT V QUALITY SYSTEMS 9

Need for ISO 9000 and other quality systems – ISO 9000:2000 quality system – Elements – Implementation of quality system – Documentation – Quality auditing – TS 16949 – ISO 14000 – Concept, requirements and benefits.

TEXT BOOKS

1. Dale H. Besterfiled, "Total Quality Management", Pearson Education, Inc. 2003.

2. James R. Evans and William M. Lidsay, "The Management and Control of Quality", 5^th Edition, South-Western, 2002.

REFERENCES

1. Feigenbaum,A.V., "Total Quality Management", McGraw Hill, 1991.

2. Oakland, J.S., "Total Quality Management", Butterworth Heineman, 1989.

3. Narayana V. and Sreenivasan, N.S., "Quality Management – Concepts and Tasks", New Age International, 1996.

4. Zeiri, "Total Quality Management for Engineers", Wood Head Publishers, 1991.

EC1451 – MOBILE AND WIRELESS COMMUNICATION

UNIT I PRINCIPLES OF WIRELESS COMMUNICATION 10

Digital modulation techniques – Linear modulation techniques – Spread spectrum modulation – Performance of modulation – Multiple access techniques – TDMA – FHMA – CDMA – SDMA – Overview of cellular networks – Cellular concept – Handoff strategies – Path loss – Fading and doppler effect.

UNIT II WIRELESS PROTOCOLS 11

Issues and challenges of wireless networks – Location management – Resource management – Routing – Power management – Security – Wireless media access techniques – ALOHA – CSMA – Wireless LAN – MAN – IEEE 802.11 (a–b–e–f–g–h–i) – Bluetooth. Wireless routing protocols – Mobile IP-IPv4-IPv6 – Wireless TCP – Protocols for 3G and 4G cellular networks – IMT-2000 – UMTS – CDMA2000 – Mobility management and handover Technologies – All-IP based cellular network

UNIT III TYPES OF WIRELESS NETWORKS 9

Mobile networks – Ad-hoc networks – Ad-hoc routing – Sensor networks – Peer-Peer networks. Mobile routing protocols – DSR – AODV – Reactive routing – Location aided routing. Mobility models – Entity based – Group mobility – Random way – Point mobility model.

UNIT IV ISSUES AND CHALLENGES 9

Issues and challenges of mobile networks – Security issues – Authentication in mobile applications – Privacy issues – Power management – Energy awareness computing. Mobile IP and Ad-hoc networks – VoIP applications.

UNIT V SIMULATION 6

Study of various network simulators (GloMoSim-NS2-Opnet) – Designing and evaluating the performance of various transport and routing protocols of mobile and wireless networks using network simulator(any one).

TEXT BOOKS

1. Theodore S. Rappaport, "Wireless Communications, Principles and Practice", PHI, 1996.

2. Stallings, W., "Wireless Communications and Networks", PHI, 2001.

REFERENCES

1. Schiller, J., "Mobile Communications", Addison Wesley, 2000.

2. Lee, W.C.Y., "Mobile Communications Engineering: Theory and Applications", 2nd Edition, TMH, 1997.

3. Pahlavan, K. and Krishnamurthy, P., "Principles of Wireless Networks", PHI, 2002.

4. Black, U.D., "Mobile and Wireless Networks", PHI, 1996.

5. Charles E. Perkins., "Ad-Hoc Networking", Addison – Wesley, 2000.

6. IEEE Journals and Proceedings

EC1011 – OPTO ELECTRONIC DEVICES

UNIT I ELEMENTS OF LIGHT AND SOLID STATE PHYSICS 9

Wave nature of light – Polarization – Interference – Diffraction – Light source – Review of quantum

mechanical concept – Review of solid state physics – Review of semiconductor physics and

semiconductor junction device.

UNIT II DISPLAY DEVICES AND LASERS 9

Introduction – Photo luminescence – Cathode luminescence – Electro luminescence – Injection

luminescence – LED – Plasma display – Liquid Crystal Displays – Numeric displays – Laser

emission – Absorption – Radiation – Population inversion – Optical feedback – Threshold condition

– Laser modes – Classes of lasers – Mode locking – Laser applications.

UNIT III OPTICAL DETECTION DEVICES 9

Photo detector – Thermal detector – Photo devices – Photo conductors – Photo diodes – Detector

performance.

UNIT IV OPTOELECTRONIC MODULATOR 9

Introduction – Analog and digital modulation – Electro-optic modulators – Magneto optic devices –

Acoustoptic devices – Optical – Switching and logic devices.

UNIT V OPTOELECTRONIC INTEGRATED CIRCUITS 9

Introduction – Hybrid and monolithic integration – Application of opto-electronic Integrated circuits

– Integrated transmitters and receivers – Guided wave devices.

Total: 45

TEXTBOOK

1. Wilson, J. and Haukes, J., "Opto Electronics – An Introduction", PHI Pvt. Ltd., 1995.

REFERENCES

1. Bhattacharya, "Semiconductor Opto Electronic Devices", PHI Pvt., Ltd., 1995.

2. Jasprit Singh, "Opto Electronics – As Introduction to Materials and Devices", TMH

International Edition, 1998.

CS1002 – DIGITAL IMAGE PROCESSING

(Common to CSE, ECE and IT)

UNIT I DIGITAL IMAGE FUNDAMENTALS AND TRANSFORMS 9

Elements of visual perception – Image sampling and quantization basic relationship between pixels – Basic Geometric transformations – Introduction to fourier transform and DFT – Properties Of 2D fourier transform – FFT – Separable image transforms – Walsh – Hadamard – Discrete cosine transform, haar, slant – Karhunen – Loeve transforms.

UNIT II IMAGE ENHANCEMENT TECHNIQUES 9

Spatial domain methods – Basic grey level transformation – Histogram equalization – Image subtraction – Image averaging – Spatial filtering: smoothing, sharpening filters – Laplacian filters – Frequency domain filters: smoothing – Sharpening filters – Homomorphic filtering.

UNIT III IMAGE RESTORATION 9

Model of image degradation/restoration process – Noise models – Inverse filtering – Least mean square filtering – Constrained least mean square filtering – Blind image restoration – Pseudo inverse – Singular value decomposition.

UNIT IV IMAGE COMPRESSION 9

Lossless compression: variable length coding – LZW coding – Bit plane coding– Predictive coding– DPCM. Lossy compression: transform Coding – Wavelet coding – Basics of image compression standards: JPEG, MPEG – Basics of vector quantization.

UNIT V IMAGE SEGMENTATION AND REPRESENTATION 9

Edge detection – Thresholding – Region based segmentation – Boundary representation: Chair codes– Polygonal approximation – Boundary segments – Boundary descriptors: Simple descriptors– Fourier descriptors – Regional descriptors – Simple descriptors– Texture.

TEXT BOOKS

1. Rafael C. Gonzalez, Richard E. Woods, "Digital Image Processing", 2nd Edition, Pearson Education, 2003.

2. William K. Pratt, "Digital Image Processing", John Willey, 2001.

REFERENCES

1. Millman Sonka, Vaclav Hlavac, Roger Boyle, Broos/Colic, Thompson Learniy, Vision, "Image Processing Analysis and Machine", 1999.

2. Jain, A.K., Phi," Fundamentals of Digital Image Processing", 1995.

3. Chanda Dutta Magundar , "Digital Image Processing and Applications", PHI, 2000.

--
  With Regards
~V Saravanan~

Mail ids :  vsara90@gmail.com
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0 Electricity Bill FOR TAMILNADU

Hi.. Friends..

Hope you are doing well..

Nowadays, technologies are very much improved.

We can pay the Electricity bill through online (*Only For Tamil Nadu) by credit/debit or net banking.

Now only the system is introduced in whole Tamil Nadu.

For this you have to register in the following website with your service no.  https://www.tnebnet.org/awp/TNEB/index.php.

Use internet explorer if you face any problem. Don't save the password in IE as well as other browsers.

You can make multiple transactions also.

I've just embedded the photo for  your reference.

--
  With Regards
~V Saravanan~

Mail ids :  vsara90@gmail.com
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My Blogs : vs90.blogspot.com
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0 Recruitment For Final Years*

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~V Saravanan~

Mail ids :  vsara90@gmail.com
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My Blogs : vs90.blogspot.com
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0 Model Questions II

HI friends...

Hope you all preparing for the sem..

I've attached d model questions 4 ur ref..
http://www.fzuploads.com/files/11/11/1289479601-vsara90-attachments.zip 

Courtesy: Praveena
-- 
  With Regards
~V Saravanan~

Mail ids :  vsara90@gmail.com
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My Blogs : vs90.blogspot.com
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0 Satellite Communication Important Questions

Hi.. Friends..

I've attached d Sat Impo. Q's.
http://www.fzuploads.com/files/11/10/1289411744-vsara90-ec1015-satellite_communication.pdf.zip

This question covers old syllabus(5 units)& new syllabus(4 units) i.e. you no need to study 5th  unit questions mentioned in the pdf. Instead of that you have to study our 5th unit -GIS material.

Courtesy: Mrs. Johnsi Rani (ECE)

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~V Saravanan~

Mail ids :  vsara90@gmail.com
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0 ECE 7th Semester Model Questions

HI friends...

Hope you all preparing for the sem..

I've attached d model questions 4 ur ref..

http://www.fzuploads.com/files/11/10/1289386564-vsara90-attachments.zip

Courtesy: Praveena

--
  With Regards
~V Saravanan~

Mail ids :  vsara90@gmail.com
               saravanan_veeran@yahoo.co.in

My Blogs : vs90.blogspot.com
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0 HAPPY DIWALI !!!

Hi. Friends..  

If u want to become a great man in the world. Spend ur life like a candle.
The festival of lights is just around the corner wish you all a Very Happy Diwali!! Let me make your Diwali more colorful with the lights of wishes of my heart. Happy Diwali!! On this diwali, I am sending you a diya of my love, I hope you will keep it lighted forver. Happy Diwali!! Happy Diwali ( I've added this video for you. Click that link) --   With Regards ~V Saravanan~ Mail ids :  vsara90@gmail.com                   saravanan_veeran@yahoo.co.in My Blogs : vs90.blogspot.com                    ecesaravanan.blogspot.com                    saravananveeran.weebly.com

0 Whats Black Box?

The "black box" is a generic term for two recording devices carried aboard commercial airliners. The Flight Data Recorder (FDR) records a variety of parameters related to the operation and flight characteristics of the plane. The Cockpit Voice Recorder (CVR) records the voices of the flight crew, engine noise, and any other sounds in the cockpit. All large commercial airliners and certain varieties of smaller commercial, corporate, and private aircraft are required by law to carry one or both of these boxes, which generally cost between $10,000 and $15,000 apiece. The data these devices provide is often invaluable to experts investigating the events leading up to an accident. The recovery of the boxes is one of the highest priorities in any mishap investigation, second only to locating survivors or recovering the remains of victims. FDR information is also often used to study other aviation safety issues, engine performance, and to identify potential maintenance 

issues.
Example of a Cockpit Voice Recorder (CVR) Despite the nickname "black box," the FDR and CVR are actually painted a bright high-visibility orange with white reflecting strips to make them easier to spot at a crash scene. The meaning of the term black box itself is somewhat unclear. Some suggest it refers to the black charring that occurs in a post-crash fire while others believe the color black is a reference to the deaths often associated with an accident investigation. The design of modern black boxes is regulated by a group called the International Civil Aviation Organization (ICAO). The ICAO determines what information the black boxes must record, over what length of time it is saved, and how survivable the boxes must be. The ICAO delegates much of this responsibility to the European Organisation for Civil Aviation Equipment (EUROCAE) that maintains a document called the Minimum Operational Performance Specification for Crash Protected Airborne Recorder Systems. Black boxes first began to appear in the 1950s and became mandatory during the 1960s. These early devices used magnetic tape for data storage, much like that used in a tape recorder. As the tape is pulled over an electromagnetic head, sound or numerical data is recorded on the medium. Analog black boxes using magnetic tape are still present aboard many planes, but these recording devices are no longer manufactured. Newer recorders instead use solid-state memory boards, called a Crash Survivable Memory Unit (CSMU), that record data in a digital format. Instead of the moving parts present in older recorders, solid-state devices use stacked arrays of memory chips similar to a USB memory stick. The lack of moving parts eases maintenance while reducing the chance of a critical component breaking in a crash. Solid-state recorders can also save considerably more data than older magnetic tape devices and are more resistant to shock, vibration, and moisture.
Magnetic tape from within the FDR of EgyptAir 990 that crashed in 1999 Whatever the medium used to record the data, the purpose of the black boxes is to collect information from various sensors aboard an aircraft. The Cockpit Voice Recorder, for example, saves sounds from microphones located on the flight deck. An area microphone is typically placed in the overhead instrument panel between the pilots, and an additional microphone is located in the headset of each member of the flight crew. These microphones pick up conversations between the flight crew, engine noises, audible warning alarms, landing gear sounds, clicks from moving switches, and any other noises like pops or thuds that might occur in the cockpit. The CVR also records communications with Air Traffic Control, automated radio weather briefings, and conversations between the pilots and ground or cabin crew. These sounds often allow investigators to determine the time of key events and system failures. Analog magnetic tape recorders are required to store four audio channels for at least 30 minutes while digital solid-state devices are required to record for two hours. Both types use continuous recording such that older information is written over as new data is collected beyond the maximum time limit.
Sample data recovered from a Flight Data Recorder The Flight Data Recorder collects data from a number of sensors to monitor information like accelerations, airspeed, altitude, heading, attitudes, cockpit control positions, thermometers, engine gauges, fuel flow, control surface positions, autopilot status, switch positions, and a variety of other parameters. Most parameters are recorded a few times per second but some FDRs can record bursts of data at higher frequencies when inputs are changing rapidly. The data measured by the different sensors is collected by the Flight Data Acquisition Unit (FDAU). This device is typically located in an equipment bay at the front of the aircraft beneath the flight deck. The FDAU assembles the desired information in the proper format and passes it on to the FDR at the rear of the plane for recording. The Federal Aviation Administration (FAA) required the FDR to record between 11 and 29 parameters, depending on aircraft size, up to 2002 but now requires saving a minimum of 88 sets of data. Analog FDRs can save a maximum of around 100 variables while digital recorders are often capable of collecting over 1,000 parameters over the course of 25 hours.
Diagram of data flow to aircraft black boxes Power for the black boxes is provided by electrical generators connected to the engines. The generators on most large airliners produce a standard output of 115 volt, 400 hertz AC power while some smaller planes instead generate 28 volt DC power. Black boxes are typically designed to use only AC or DC power but not either one. Recorders built for compatibility with the AC power supplies on larger planes cannot be used on small DC-powered aircraft. In the event of engine failure, larger aircraft are also equipped with emergency backup power sources like the auxiliary power generator and ram air turbine to continue operating the black boxes. In addition, the ICAO is considering making a battery mandatory on solid-state recorders to provide an independent power supply in the event of a complete power failure aboard the plane. A common misconception states that the black boxes are "indestructible." No manmade device is indestructible, and no material has ever been developed that cannot be destroyed under severe enough conditions. The black boxes are instead designed to be highly survivable in a crash. In many of the worst aviation accidents, the only devices to survive in working order are the Crash Survivable Memory Units (CSMUs) in the black boxes. The remainder of the recorders, including the external case and other internal components, are often heavily damaged.
Interior cut-away of a black box design The CSMU, however, is contained within a very compact cylindrical or rectangular box designed to safeguard the data within against extreme conditions. The box is composed of three layers to provide different types of protection to the recording medium. The outermost shell is a case made of hardened steel or titanium designed to survive intense impact and pressure damage. The second layer is an insulation box while the third is a thermal block to protect against severe fire and heat. Together, these three layered cases allow the FDR and CVR to survive in all but the most extreme crash conditions. Current regulations require the black boxes to survive an impact of 3,400 g's for up to 6.5 milliseconds. This rapid deceleration is equivalent to slowing from a speed of 310 miles per hour (500 km/h) to a complete stop in a distance of just 18 inches (45 cm). This requirement is tested by firing the CSMU from an air cannon to demonstrate the device can withstand an impact force at least 3,400 times its own weight. The black boxes must also survive a penetration test during which a steel pin dropped from a height of 10 ft (3 m) impacts the CSMU at its most vulnerable point with a force of 500 pounds (2,225 N). In addition, a static crush test is conducted to demonstrate that all sides of the CSMU can withstand a pressure of 5,000 pounds per square inch (350 kg/cm�) for five minutes. The fire resistance of the CSMU is further tested by exposing it to a temperature of 2,000�F (1,100�C) for up to an hour. The device is also required to survive after lying in smoldering wreckage for ten hours at a temperature of 500�F (260�C).
Underwater Locator Beacon on a black box Other requirements specify survivability limits when immersed in liquids. The CSMU must endure the water pressure found at an ocean depth of 20,000 ft (6,100 m), and a deep-sea submersion test is conducted for 24 hours. Another saltwater submersion test lasting 30 days demonstrates both the survivability of the CSMU and the function of an Underwater Locator Beacon (ULB), or "pinger," that emits an ultrasonic signal once a second when immersed in water. These signals can be transmitted as deep 14,000 ft (4,270 m) and are detectable by sonar to help locate the recorders. A final series of tests includes submerging the CSMU in various fluids like jet fuel and fire extinguishing chemicals to verify the device can withstand the corrosive effects of such liquids. Upon completion of the testing, the black boxes are disassembled and the CSMU boards are extracted. The boards are then reassembled in a new case and attached to a readout system to verify that the pre-recorded data written to the device can still be read and processed. Another factor important to the survivability of the black boxes is their installation in the tail of the aircraft. The exact location often varies depending on the plane, but the FDR and CVR are usually placed near the galley, in the aft cargo hold, or in the tail cone. The recorders are stored in the tail since this is usually the last part of the aircraft to impact in an accident. The entire front portion of the plane acts like a crush zone that helps to decelerate the tail more slowly. This effect reduces the shock experienced by the recorders and helps to cushion the devices to improve their chances of surviving the crash.
Flight Data Recorder recovered from United Airlines 93 in 2001 Once the black boxes have been located following an accident, they are typically taken into custody by an aviation safety agency for analysis. In the United States, responsibility for investigating most air accidents belongs to the National Transportation Safety Board (NTSB). Many countries lacking the capability to analyze black boxes also send their recorders to the computer labs of the NTSB or some of the better-equipped investigative organizations in Western nations. Care must be taken in recovering and transporting the recorders so that no further damage is done to the devices that might prevent important data from being extracted. Upon receipt of the recorders, the NTSB uses a series of computer and audio equipment to process and analyze any information that can be recovered. The data is translated into formats readily usable by investigators and is usually critical in identifying the probable cause(s) of the accident. This process may take many weeks or months depending on the condition of the black boxes and the level of processing required to make sense of the data. Outside experts are also often consulted to help analyze and interpret the data.

Animation image created using FDR data from American Airlines 587 that crashed in 2001
Flight Data Recorder information is typically presented in the form of graphs or animations used to understand instrument readings, flight characteristics, and the performance of the aircraft during its final moments. Cockpit Voice Recorder information is usually more sensitive and laws strictly regulate how it is handled. A committee including representatives of the NTSB, FAA, the airline, the manufacturers of the aircraft and engines, and the pilots union is responsible for preparing a transcript of the CVR's contents. This transcript is painstakingly created using air traffic control logs and sound spectrum analysis software to provide exact timing. Although the transcript can be released to the public, only select and pertinent portions of the actual audio recording are made public due to privacy concerns.
Flight recorder design has improved considerably since the devices were first introduced in the 1950s. However, no recording device is perfect. Black boxes are sometimes never found or too badly damaged to recover some or all of the data from a crash. To reduce the likelihood of damage or loss, some more recent designs are self-ejecting and use the energy of impact to separate themselves from the aircraft. Loss of electrical power is also a common event in aviation accicents, such as Swissair Flight 111 when the black boxes were inoperative for the last six minutes of flight due to aircraft power failure. Several safety organizations have recommended providing the recorders with a backup battery to operate the devices for up to ten minutes if power is interrupted.

Cockpit Voice Recorder recovered from United Airlines 93 in 2001
Another recommendation is to add a second independent set of recorders on a separate electrical bus to insure redundancy in the event of a system failure. The additional recorders would be located as close to the cockpit as possible while the existing black boxes remain in the tail to reduce the likelihood of a single failure incapacitating both sets. Accident investigators have also argued for the installation of a third black box to record cockpit video. Though pilots have so far resisted the move because of privacy issues, video data would be useful to better understand pilot actions in the moments leading up to an accident.












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With Regards
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Mail ids : vsara90@gmail.com
saravanan_veeran@yahoo.co.in

My Blogs : vs90.blogspot.com
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0 Optical Communication and Networks Model Question Papers for 7th ECE

Hi friends....

Here s link for OCN model question papers..
http://www.fzuploads.com/files/10/20/1287598234-vsara90-MODEL_QUESTION_PAPERS.pdf

Courtesy: Mrs. K. Ambujam Asst. Prof (ECE) @ JJCET

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Mail ids :  vsara90@gmail.com
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My Blogs : vs90.blogspot.com
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0 Introduction to ARM thumb

Many complex functions that are performed in a single, albeit slow, instruction in a CISC processor may require multiple instructions in a RISC. To reduce the memory costs of these extra instructions, consider a processor with Thumb. Many of today's most popular 32-bit microcontrollers use RISC technology. Unlike CISC processors, RISC engines generally execute each instruction in a single clock cycle, which typically results in faster execution than on a CISC processor with the same clock speed.
Increased performance, however, comes at a price: a RISC processor typically needs more memory than a CISC does to store the same program. Many of the complex functions performed in a single, albeit slow, instruction in a CISC processor may require two, three, or more simpler instructions in a RISC.
Except in the most speed-critical of embedded devices, the cost of memory is much more critical than the execution speed of the processor. To reduce memory requirements and, thereby, cost, Advanced RISC Machines (ARM) created the Thumb instruction set as an option for their RISC processor cores. The most well-known chip that includes the Thumb instruction set is the ARM7TDMI. The "T" in the core's full name specifies Thumb.
Size matters
The Thumb instruction set consists of 16-bit instructions that act as a compact shorthand for a subset of the 32-bit instructions of the standard ARM. Every Thumb instruction could instead be executed via the equivalent 32-bit ARM instruction. However, not all ARM instructions are available in the Thumb subset; for example, there's no way to access status or coprocessor registers. Also, some functions that can be accomplished in a single ARM instruction can only be simulated with a sequence of Thumb instructions.
At this point, you may ask why have two instruction sets in the same CPU? But really the ARM contains only one instruction set: the 32-bit set. When it's operating in the Thumb state, the processor simply expands the smaller shorthand instructions fetched from memory into their 32-bit equivalents.
The difference between two equivalent instructions lies in how the instructions are fetched and interpreted prior to execution, not in how they function. Since the expansion from 16-bit to 32-bit instruction is accomplished via dedicated hardware within the chip, it doesn't slow execution even a bit. But the narrower 16-bit instructions do offer memory advantages.
The Thumb instruction set provides most of the functionality required in a typical application. Arithmetic and logical operations, load/store data movements, and conditional and unconditional branches are supported. Based upon the available instruction set, any code written in C could be executed successfully in Thumb state. However, device drivers and exception handlers must often be written at least partly in ARM state.
Register sets
When operating in the 16-bit Thumb state, the application encounters a slightly different set of registers. Figure 1 compares the programmer's model in that state to the same model in the 32-bit ARM state.

Figure 1 ARM vs. Thumb programmer's models
In the ARM state, 17 registers are visible in user mode. One additional register—a saved copy of Current Program Status Register (CPSR) that's called SPSR (Saved Program Status Register)—is for exception mode only.
Notice that the 12 registers accessible in Thumb state are exactly the same physical 32-bit registers accessible in ARM state. Thus data can be passed between software running in the ARM state and software running in the Thumb state via registers R0 through R7. This is done frequently in actual applications.
The biggest register difference involves the SP register. The Thumb state has unique stack mnemonics (PUSH, POP) that don't exist in the ARM state. These instructions assume the existence of a stack pointer, for which R13 is used. They translate into load and store instructions in the ARM state.
The CPSR register holds the processor mode (user or exception flag), interrupt mask bits, condition codes, and Thumb status bit. The Thumb status bit (T) indicates the processor's current state: 0 for ARM state (default) or 1 for Thumb. Although other bits in the CPSR may be modified in software, it's dangerous to write to T directly; the results of an improper state change are unpredictable.
Thumbs up
There are several ways to enter or leave the Thumb state properly. The usual method is via the Branch and Exchange (BX) instruction. See also Branch, Link, and Exchange (BLX) if you're using an ARM with version 5 architecture. During the branch, the CPU examines the least significant bit (LSb) of the destination address to determine the new state. Since all ARM instructions will align themselves on either a 32- or 16-bit boundary, the LSB of the address is not used in the branch directly. However, if the LSB is 1 when branching from ARM state, the processor switches to Thumb state before it begins executing from the new address; if 0 when branching from Thumb state, back to ARM state it goes.
Listing 1: How to change into Thumb state, then back

	mov	R0,#5	;Argument to function is in R0
	add	R1,PC,#1	;Load address of SUB_BRANCH, Set for THUMB by adding 1
	BX	R1	;R1 contains address of SUB_BRANCH+1
;Assembler-specific instruction to switch to Thumb SUB_BRANCH:
	BL	thumb_sub	;Must be in a space of +/- 4 MB
	add	R1,#7	;Point to SUB_RETURN with bit 0 clear
	BX	R1
;Assembler-specific instruction to switch to ARM SUB_RETURN:

Listing 1 shows one example (not the only one) of using the BX instruction to go from ARM to Thumb state and back. This example first switches to Thumb state, then calls a subroutine that was written in Thumb code. Upon return from the subroutine, the system again switches back to ARM state; though this assumes that R1 is preserved by the subroutine. The PC always contains the address of the instruction that is being executed plus 8 (which happens to be SUB_BRANCH). The Thumb BL instruction actually resolves into two instructions, so 8 bytes are used between SUB_BRANCH and SUB_RETURN.
When an exception occurs, the processor automatically begins executing in ARM state at the address of the exception vector. So another way to change state is to place your 32-bit code in an exception handler. If the CPU is running in Thumb state when that exception occurs, you can count on it being in ARM state within the handler. If desired, you can have the exception handler put the CPU into Thumb state via a branch.
The final way to change the state is via a return from exception. When returning from the processor's exception mode, the saved value of T in the SPSR register is used to restore the state. This bit can be used, for example, by an operating system to manually restart a task in the Thumb state—if that's how it was running previously.
Put your thumb out
The biggest reason to look for an ARM processor with the Thumb instruction set is if you need to reduce code density. In addition to reducing the total amount of memory required, you may also be able to narrow the data bus to just 16 bits. With the narrower bus, it will take two bus cycles to fetch a single 32-bit instruction; but you'll only pay that penalty in the parts of your code that can't be implemented with the Thumb instructions. And you'll still have the benefits of a powerful 32-bit RISC processor. A nifty trick indeed. 


Thanks to Joe Lemieux

0 Thumb 2

Improved Code Density with Performance and Power Efficiency

Thumb-2 technology is the instruction set underlying the ARM Cortex architecture which provides enhanced levels of performance, energy efficiency, and code density for a wide range of embedded applications.
Thumb-2 technology builds on the success of Thumb, the innovative high code density instruction set for ARM microprocessor cores, to increase the power of the ARM microprocessor core available to developers of low cost, high performance systems.
The technology is backwards compatible with existing ARM and Thumb solutions, while significantly extending the features available to the Thumb instructions set. This allows more of the application to benefit from the best in class code density of Thumb.
For performance optimised code Thumb-2 technology uses 31 percent less memory to reduce system cost, while providing up to 38 percent higher performance than existing high density code, which can be used to prolong battery-life or to enrich the product feature set. Thumb-2 technology is featured in the  processor, and in all ARMv7 architecture-based processors.

0 Thumb 1

With cost-sensitive embedded control applications such as cell phones, disk drives, modems and pagers all hitting the performance ceilings of their current generation CISC controllers, designers are looking for ways to achieve 32-bit performance and address space but without the costs associated with going to a 32-bit system.

Thumb offers the designer

• Excellent code-density for minimal system memory size and cost 32-bit performance from 8- or16-bit memory on an 8- or 16-bit bus for low system cost.
• Plus the established ARM features
• Industry-leading MIPS/Watt for maximum battery life and RISC performance
• Small die size for integration and minimum chip cost
• Global multi-partner sourcing for secure supply.

Thumb technology is an extension to the 32-bit ARM architecture. The Thumb instruction set features a subset of the most commonly used 32-bit ARM instructions which have been compressed into 16-bit wide opcodes. On execution, these 16-bit instructions are decompressed transparently to full 32-bit ARM instructions in real time without performance loss.
Designers can use both 16-bit Thumb and 32-bit ARM instructions sets and therefore have the flexibility to emphasise performance or code size on a sub-routine level as their applications require.
A "Thumb-aware" core is a standard ARM processor fitted with a Thumb decompressor in the instruction pipeline. The designer therefore gets all the underlying power of the 32-bit ARM architecture as well as excellent code density from Thumb, all at 8-bit system cost.
Thumb has better code density than common 8 and 16-bit CISC/RISC Controllers and is at a fraction of the code size of traditional 32-bit architectures. This means that program memory can be smaller and hence cost reduced.
The Thumb architecture is supported by a complete Windows software development environment as well as development and evaluation cards.

0 ARM

The ARM 32-bit instruction set is the base 32-bit ISA used in the ARMv4T, ARMv5TEJ and ARMv6 architectures.  In these architectures it is used in applications requiring high performance, or for handling hardware exceptions such as interrupts and processor start-up.

The ARM 32-bit ISA is also supported in the Cortex™-A and Cortex-R profiles of the Cortex architecture for performance critical applications, and for legacy code.  Most of its functionality is subsumed into the Thumb-2 instruction set, which also benefits from improved code density.

ARM instructions are 32-bits wide, and are aligned on 4-byte boundaries.

All ARM instructions can also be "conditionalised" to only execute when previous instructions have set a particular condition code. This means that instructions only have their normal effect on the programmers’ model operation, memory and coprocessors if the N, Z, C and V flags in the Application Program Status Register satisfy a condition specified in the instruction. If the flags do not satisfy this condition, the instruction acts as a NOP, that is, execution advances to the next instruction as normal, including any relevant checks for exceptions being taken, but has no other effect.  This conditionalisation of instructions allows small sections of if- and while-statements to be encoded without the use of branch instructions.

The condition codes are:

Condition Code	Meaning
N	Negative condition code, set to 1 if  result is negative
Z	Zero condition code, set to 1 if the result of the instruction is 0
C	Carry condition code, set to 1 if the instruction results in a carry condition
V	Overflow condition code, set to 1 if the instruction results in an overflow condition.

0 Instruction Set Architectures

The ARM processor architecture provides support for the 32-bit ARM and 16-bit Thumb^® Instruction Set Architectures (ISAs) along with architecture extensions to provide support for Java acceleration (Jazelle®), security (TrustZone®), SIMD, and NEON™ technologies.The ARM architecture supports implementations across a wide range of performance points. It is established as the dominant architecture in many market segments. The architectural simplicity of ARM processors leads to very small implementations, and small implementations mean devices can have very low power consumption. Implementation size, performance, and very low power consumption are key attributes of the ARM architecture.
The ARM architecture is a Reduced Instruction Set Computer (RISC) architecture, as it incorporates these typical RISC architecture features:

• Large uniform register file
• Load/store architecture, where data-processing operations only operate on register contents, not directly on memory contents
• Simple addressing modes, with all load/store addresses being determined from register contents and instruction fields only.

In addition, the ARM architecture provides:

• Instructions that combine a shift with an arithmetic or logical operation
• Auto-increment and auto-decrement addressing modes to optimize program loops
• Load and Store Multiple instructions to maximize data throughput
• Conditional execution of almost all instructions to maximize execution throughput.

These enhancements to a basic RISC architecture enable ARM processors to achieve a good balance of high performance, small code size, low power consumption, and small silicon area.
The ARM Instruction Architecture is constantly improving to meet the increasing demands of leading edge applications developers, while retaining the backwards compatibility necessary to protect investment in software development.
ARM uses the Universal Assembly Language to provide a canonical form for all ARM and Thumb instructions.  This allows the user to write assembly code which can be assembled for either instruction set.

0 Satellite V unit material

Hi Friends....

Hope you all preparing for the Semester..

I've enclosed the link for the Satellite communication Vth Unit materials...

http://www.fzuploads.com/files/10/14/1287075507-vsara90-satellite_v_unit.doc.zip

(Change the font size n take print out)
Password to open : student

Reply me if there any problem in this document.

Courtesy: Mrs. Johnsi Rani, (ECE) Ass. Prof in JJCET

--
  With Regards
~V Saravanan~

Mail ids :  vsara90@gmail.com
               saravanan_veeran@yahoo.co.in

My Blogs : vs90.blogspot.com
                 ecesaravanan.blogspot.com
                 saravananveeran.weebly.com

0 System Design Lab Prog.

SQUARE WAVE
.MMREGS
.TEXT
ldp #100h
splk #7FFH,00h
l3: out 00H,04h
call l1
splk #0FFH,01h
out 01h,04h
call l1
b l3
l1: lar ar3,#0FFh
l2: mar *,ar3
banz l2,*-
ret

TRIANGULAR
ldp #100h
splk #00h,00h
l3: lar ar2,#45h
l1: out 00h,04h
lacc 00h
add #15h
sacl 00h
mar *,ar2
banz l1,*-
lar ar2,#45h
l2: out 00h,04
lacc 00h
sub #15h
sacl 00h
mar *,ar2
banz l2 b l3

Hi.. Friends..

I've posted d program for triangular and square wave generation..



SQUARE WAVE
         .MMREGS
         .TEXT
         ldp #100h
         splk #7FFH,00h
l3:     out 00H,04h
        call l1
        splk #0FFH,01h
        out 01h,04h
        call l1
        b  l3
l1:    lar ar3,#0FFh
l2:    mar *,ar3
        banz l2,*-
        ret

TRIANGULAR
       ldp #100h
       splk #00h,00h
l3:    lar ar2,#45h
l1:    out 00h,04h
       lacc 00h
       add #15h
       sacl 00h
       mar *,ar2
       banz l1,*-
       lar ar2,#45h
l2:    out 00h,04
       lacc 00h
       sub #15h
       sacl 00h
       mar *,ar2   
       banz l2
       b l3


This is d program hav to enter on to the kit..

Dont need to write old programs with opcode in exam..

(If you've written correctly ignore it)

--
  With Regards
~V Saravanan~

Mail ids :  vsara90@gmail.com
               saravanan_veeran@yahoo.co.in

My Blogs : vs90.blogspot.com
                 ecesaravanan.blogspot.com
                 saravananveeran.weebly.com

0 Embedded Lab Programs

Hi friends...

I've just posted link for the Embedded lab programs...
It contains all d programs for our exam.. I've highlighted some words in that, those coding must be known to us.

Password to open: student
http://www.fzuploads.com/files/10/14/1287073397-vsara90-EMBEDDED_LAB_PROGRAMS_FULL.pdf.zip

If you've any problem in that, then mail me...
--
  With Regards
~V Saravanan~

Mail ids :  vsara90@gmail.com
               saravanan_veeran@yahoo.co.in

My Blogs : vs90.blogspot.com
                 ecesaravanan.blogspot.com
                 saravananveeran.weebly.com

0 Optical Model Question Papers

Hi friends..

                I've attached d question for the optical exam.. Pass to all........                                               
Here r d links..
http://www.novaup.com/download/7m4e2cft5pf3g

http://www.easy-share.com/1912488196/MODEL QUESTION PAPERS.pdf

 http://uploading.com/files/1b6cm33b/MODEL%2BQUESTION%2BPAPERS.pdf/
--

Password to open: student

0 CWG, Delhi 2010.......Lets support GAMES first..!!

Friends,

Successful completion of CWG is a must for INDIA's image….

There has been so much negative publicity about it….let's support the games now, and for sure it doesn't mean that we support the corruption involved with it,we are supporting INDIA!!!!

See Below Pictures..........

CWG Stadiums, Delhi, India

Jai Hind

 

--
  With Regards
   ~INDIAN~

Mail ids :  vsara90@gmail.com
               saravanan_veeran@yahoo.co.in

My Blogs : vs90.blogspot.com
                 ecesaravanan.blogspot.com
                 saravananveeran.weebly.com