The ARM 32-bit ISA is also supported in the Cortex™-A and Cortex-R profiles of the Cortex architecture for performance critical applications, and for legacy code. Most of its functionality is subsumed into the Thumb-2 instruction set, which also benefits from improved code density.
ARM instructions are 32-bits wide, and are aligned on 4-byte boundaries.
All ARM instructions can also be "conditionalised" to only execute when previous instructions have set a particular condition code. This means that instructions only have their normal effect on the programmers’ model operation, memory and coprocessors if the N, Z, C and V flags in the Application Program Status Register satisfy a condition specified in the instruction. If the flags do not satisfy this condition, the instruction acts as a NOP, that is, execution advances to the next instruction as normal, including any relevant checks for exceptions being taken, but has no other effect. This conditionalisation of instructions allows small sections of if- and while-statements to be encoded without the use of branch instructions.
The condition codes are:| Condition Code | Meaning |
|---|---|
N | Negative condition code, set to 1 if result is negative |
Z | Zero condition code, set to 1 if the result of the instruction is 0 |
C | Carry condition code, set to 1 if the instruction results in a carry condition |
V | Overflow condition code, set to 1 if the instruction results in an overflow condition. |
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