module traffic(clk, rst, ls, ss, sw, sn, se, rs, red_s, ys, ps_r, ps_g);
input clk;
input rst;
output ls;
output ss;
output sw;
output sn;
output se;
output rs;
output red_s;
output ys;
output ps_r;
output ps_g;
reg ls;
reg ss,sw,sn,se;
reg rs;
reg red_s,red_e;
reg ys;
reg ps_r;
reg ps_g;
reg [3:0]ps,ns;
reg [31:0]div;
reg [3:0]cnt;
wire clk_s;
parameter[3:0]start=4'b0000;
parameter[3:0]south_g=4'b0001;
parameter[3:0]south_orange=4'b0010;
parameter[3:0]south_r=4'b0011;
parameter[3:0]west_g=4'b0100;
parameter[3:0]west_orange=4'b0101;
parameter[3:0]west_r=4'b0110;
parameter[3:0]east_g=4'b0111;
parameter[3:0]east_orange=4'b1000;
parameter[3:0]east_r=4'b1001;
parameter[3:0]north_g=4'b1010;
parameter[3:0]north_orange=4'b1011;
parameter[3:0]north_r=4'b1100;
always@(posedge clk or posedge rst)
begin
if(rst)
div<=2'b00;
else
div<=div+1;
end
assign clk_s=div[20];
always@(posedge clk_s or posedge rst)
begin
if(rst)
cnt<=4'b0;
else
cnt<=cnt+1;
end
always@(posedge clk_s or posedge rst)
begin
if(rst)
ps<=start;
else
ps<=ns;
end
always @(ps)
case(ps)
start:ns<=south_g;
south_g:begin
if(cnt==10)
ns<=south_orange;
else
ns<=south_g;
end
south_orange:begin
if(cnt==14)
ns<=south_r;
else
ns<=south_orange;
end
south_r:begin
if(cnt==15)
ns<=west_g;
else
ns<=south_r;
end
default:ns<=start;
endcase
always@(ps)
begin
red_s<=0;
rs<=0;
ss<=0;sw<=0;sn<=0;se<=0 ;
ls<=0;
ps_g<=0;
ys<=0;
ps_r<=0;
case(ps)
start:begin
red_s<=1;
end
south_g:begin
ls<=1;
rs<=1;
ss<=1;
ps_r<=1;
end
south_orange:begin
ls<=1;
ys<=1;
ps_r<=1;
end
south_r:begin
ls<=1;
red_e<=1;
ps_r<=1;
end
west_g:begin
ls<=1;
red_s<=1;
ps_r<=1;
end
west_orange:begin
ls<=1;
red_s<=1;
ps_r<=1;
end
west_r:begin
red_s<=1;
ps_r<=1;
end
north_g:begin
sn<=1;
red_s<=1;
ps_r<=1;
end
north_orange:begin
ps_g<=1;
red_s<=1;
end
north_r:begin
red_s<=1;
ps_r<=1;
end
east_g:begin
se<=1;
red_s<=1;
ps_r<=1;
end
east_orange:begin
red_s<=1;
ps_r<=1;
end
east_r:begin
red_s<=1;
ps_r<=1;
end
default:begin
red_s<=0;
rs<=0;
ss<=0;sw<=0;sn<=0;se<=0;
ls<=0;
ps_g<=0;
ys<=0;
ps_r<=0;
end
endcase
end
endmodule
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