0 Embedded Systems Ex no. 1

module pg(a,b,in,ps,ns,y);
input[3:0] a,b;
input in;
input [1:0] ps;
output y;
output [1:0]ns;
reg y;
always@(in or a or b)
begin
if(in==1)
if(ps==2'b00)
ns=2'b01;
else if(ps==2'b01)
ns=2'b11;
else if(ps==2'b11)
ns=2'b10;
else (ns==ps)
case(ns)
2'b00:y=a+b;
2'b01:y=a^b;
2'b11:y=a-b;
2'b10:y=a*b;
endcase
endmodule

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