0 Optical Communication and Networks Model Question Papers for 7th ECE

Hi friends....

Here s link for OCN model question papers..
http://www.fzuploads.com/files/10/20/1287598234-vsara90-MODEL_QUESTION_PAPERS.pdf

Courtesy: Mrs. K. Ambujam Asst. Prof (ECE) @ JJCET

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~V Saravanan~

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0 Introduction to ARM thumb

Many complex functions that are performed in a single, albeit slow, instruction in a CISC processor may require multiple instructions in a RISC. To reduce the memory costs of these extra instructions, consider a processor with Thumb. Many of today's most popular 32-bit microcontrollers use RISC technology. Unlike CISC processors, RISC engines generally execute each instruction in a single clock cycle, which typically results in faster execution than on a CISC processor with the same clock speed.
Increased performance, however, comes at a price: a RISC processor typically needs more memory than a CISC does to store the same program. Many of the complex functions performed in a single, albeit slow, instruction in a CISC processor may require two, three, or more simpler instructions in a RISC.
Except in the most speed-critical of embedded devices, the cost of memory is much more critical than the execution speed of the processor. To reduce memory requirements and, thereby, cost, Advanced RISC Machines (ARM) created the Thumb instruction set as an option for their RISC processor cores. The most well-known chip that includes the Thumb instruction set is the ARM7TDMI. The "T" in the core's full name specifies Thumb.
Size matters
The Thumb instruction set consists of 16-bit instructions that act as a compact shorthand for a subset of the 32-bit instructions of the standard ARM. Every Thumb instruction could instead be executed via the equivalent 32-bit ARM instruction. However, not all ARM instructions are available in the Thumb subset; for example, there's no way to access status or coprocessor registers. Also, some functions that can be accomplished in a single ARM instruction can only be simulated with a sequence of Thumb instructions.
At this point, you may ask why have two instruction sets in the same CPU? But really the ARM contains only one instruction set: the 32-bit set. When it's operating in the Thumb state, the processor simply expands the smaller shorthand instructions fetched from memory into their 32-bit equivalents.
The difference between two equivalent instructions lies in how the instructions are fetched and interpreted prior to execution, not in how they function. Since the expansion from 16-bit to 32-bit instruction is accomplished via dedicated hardware within the chip, it doesn't slow execution even a bit. But the narrower 16-bit instructions do offer memory advantages.
The Thumb instruction set provides most of the functionality required in a typical application. Arithmetic and logical operations, load/store data movements, and conditional and unconditional branches are supported. Based upon the available instruction set, any code written in C could be executed successfully in Thumb state. However, device drivers and exception handlers must often be written at least partly in ARM state.
Register sets
When operating in the 16-bit Thumb state, the application encounters a slightly different set of registers. Figure 1 compares the programmer's model in that state to the same model in the 32-bit ARM state.

Figure 1 ARM vs. Thumb programmer's models
In the ARM state, 17 registers are visible in user mode. One additional register—a saved copy of Current Program Status Register (CPSR) that's called SPSR (Saved Program Status Register)—is for exception mode only.
Notice that the 12 registers accessible in Thumb state are exactly the same physical 32-bit registers accessible in ARM state. Thus data can be passed between software running in the ARM state and software running in the Thumb state via registers R0 through R7. This is done frequently in actual applications.
The biggest register difference involves the SP register. The Thumb state has unique stack mnemonics (PUSH, POP) that don't exist in the ARM state. These instructions assume the existence of a stack pointer, for which R13 is used. They translate into load and store instructions in the ARM state.
The CPSR register holds the processor mode (user or exception flag), interrupt mask bits, condition codes, and Thumb status bit. The Thumb status bit (T) indicates the processor's current state: 0 for ARM state (default) or 1 for Thumb. Although other bits in the CPSR may be modified in software, it's dangerous to write to T directly; the results of an improper state change are unpredictable.
Thumbs up
There are several ways to enter or leave the Thumb state properly. The usual method is via the Branch and Exchange (BX) instruction. See also Branch, Link, and Exchange (BLX) if you're using an ARM with version 5 architecture. During the branch, the CPU examines the least significant bit (LSb) of the destination address to determine the new state. Since all ARM instructions will align themselves on either a 32- or 16-bit boundary, the LSB of the address is not used in the branch directly. However, if the LSB is 1 when branching from ARM state, the processor switches to Thumb state before it begins executing from the new address; if 0 when branching from Thumb state, back to ARM state it goes.
Listing 1: How to change into Thumb state, then back

	mov	R0,#5	;Argument to function is in R0
	add	R1,PC,#1	;Load address of SUB_BRANCH, Set for THUMB by adding 1
	BX	R1	;R1 contains address of SUB_BRANCH+1
;Assembler-specific instruction to switch to Thumb SUB_BRANCH:
	BL	thumb_sub	;Must be in a space of +/- 4 MB
	add	R1,#7	;Point to SUB_RETURN with bit 0 clear
	BX	R1
;Assembler-specific instruction to switch to ARM SUB_RETURN:

Listing 1 shows one example (not the only one) of using the BX instruction to go from ARM to Thumb state and back. This example first switches to Thumb state, then calls a subroutine that was written in Thumb code. Upon return from the subroutine, the system again switches back to ARM state; though this assumes that R1 is preserved by the subroutine. The PC always contains the address of the instruction that is being executed plus 8 (which happens to be SUB_BRANCH). The Thumb BL instruction actually resolves into two instructions, so 8 bytes are used between SUB_BRANCH and SUB_RETURN.
When an exception occurs, the processor automatically begins executing in ARM state at the address of the exception vector. So another way to change state is to place your 32-bit code in an exception handler. If the CPU is running in Thumb state when that exception occurs, you can count on it being in ARM state within the handler. If desired, you can have the exception handler put the CPU into Thumb state via a branch.
The final way to change the state is via a return from exception. When returning from the processor's exception mode, the saved value of T in the SPSR register is used to restore the state. This bit can be used, for example, by an operating system to manually restart a task in the Thumb state—if that's how it was running previously.
Put your thumb out
The biggest reason to look for an ARM processor with the Thumb instruction set is if you need to reduce code density. In addition to reducing the total amount of memory required, you may also be able to narrow the data bus to just 16 bits. With the narrower bus, it will take two bus cycles to fetch a single 32-bit instruction; but you'll only pay that penalty in the parts of your code that can't be implemented with the Thumb instructions. And you'll still have the benefits of a powerful 32-bit RISC processor. A nifty trick indeed. 


Thanks to Joe Lemieux

0 Thumb 2

Improved Code Density with Performance and Power Efficiency

Thumb-2 technology is the instruction set underlying the ARM Cortex architecture which provides enhanced levels of performance, energy efficiency, and code density for a wide range of embedded applications.
Thumb-2 technology builds on the success of Thumb, the innovative high code density instruction set for ARM microprocessor cores, to increase the power of the ARM microprocessor core available to developers of low cost, high performance systems.
The technology is backwards compatible with existing ARM and Thumb solutions, while significantly extending the features available to the Thumb instructions set. This allows more of the application to benefit from the best in class code density of Thumb.
For performance optimised code Thumb-2 technology uses 31 percent less memory to reduce system cost, while providing up to 38 percent higher performance than existing high density code, which can be used to prolong battery-life or to enrich the product feature set. Thumb-2 technology is featured in the  processor, and in all ARMv7 architecture-based processors.

0 Thumb 1

With cost-sensitive embedded control applications such as cell phones, disk drives, modems and pagers all hitting the performance ceilings of their current generation CISC controllers, designers are looking for ways to achieve 32-bit performance and address space but without the costs associated with going to a 32-bit system.

Thumb offers the designer

• Excellent code-density for minimal system memory size and cost 32-bit performance from 8- or16-bit memory on an 8- or 16-bit bus for low system cost.
• Plus the established ARM features
• Industry-leading MIPS/Watt for maximum battery life and RISC performance
• Small die size for integration and minimum chip cost
• Global multi-partner sourcing for secure supply.

Thumb technology is an extension to the 32-bit ARM architecture. The Thumb instruction set features a subset of the most commonly used 32-bit ARM instructions which have been compressed into 16-bit wide opcodes. On execution, these 16-bit instructions are decompressed transparently to full 32-bit ARM instructions in real time without performance loss.
Designers can use both 16-bit Thumb and 32-bit ARM instructions sets and therefore have the flexibility to emphasise performance or code size on a sub-routine level as their applications require.
A "Thumb-aware" core is a standard ARM processor fitted with a Thumb decompressor in the instruction pipeline. The designer therefore gets all the underlying power of the 32-bit ARM architecture as well as excellent code density from Thumb, all at 8-bit system cost.
Thumb has better code density than common 8 and 16-bit CISC/RISC Controllers and is at a fraction of the code size of traditional 32-bit architectures. This means that program memory can be smaller and hence cost reduced.
The Thumb architecture is supported by a complete Windows software development environment as well as development and evaluation cards.

0 ARM

The ARM 32-bit instruction set is the base 32-bit ISA used in the ARMv4T, ARMv5TEJ and ARMv6 architectures.  In these architectures it is used in applications requiring high performance, or for handling hardware exceptions such as interrupts and processor start-up.

The ARM 32-bit ISA is also supported in the Cortex™-A and Cortex-R profiles of the Cortex architecture for performance critical applications, and for legacy code.  Most of its functionality is subsumed into the Thumb-2 instruction set, which also benefits from improved code density.

ARM instructions are 32-bits wide, and are aligned on 4-byte boundaries.

All ARM instructions can also be "conditionalised" to only execute when previous instructions have set a particular condition code. This means that instructions only have their normal effect on the programmers’ model operation, memory and coprocessors if the N, Z, C and V flags in the Application Program Status Register satisfy a condition specified in the instruction. If the flags do not satisfy this condition, the instruction acts as a NOP, that is, execution advances to the next instruction as normal, including any relevant checks for exceptions being taken, but has no other effect.  This conditionalisation of instructions allows small sections of if- and while-statements to be encoded without the use of branch instructions.

The condition codes are:

Condition Code	Meaning
N	Negative condition code, set to 1 if  result is negative
Z	Zero condition code, set to 1 if the result of the instruction is 0
C	Carry condition code, set to 1 if the instruction results in a carry condition
V	Overflow condition code, set to 1 if the instruction results in an overflow condition.

0 Instruction Set Architectures

The ARM processor architecture provides support for the 32-bit ARM and 16-bit Thumb^® Instruction Set Architectures (ISAs) along with architecture extensions to provide support for Java acceleration (Jazelle®), security (TrustZone®), SIMD, and NEON™ technologies.The ARM architecture supports implementations across a wide range of performance points. It is established as the dominant architecture in many market segments. The architectural simplicity of ARM processors leads to very small implementations, and small implementations mean devices can have very low power consumption. Implementation size, performance, and very low power consumption are key attributes of the ARM architecture.
The ARM architecture is a Reduced Instruction Set Computer (RISC) architecture, as it incorporates these typical RISC architecture features:

• Large uniform register file
• Load/store architecture, where data-processing operations only operate on register contents, not directly on memory contents
• Simple addressing modes, with all load/store addresses being determined from register contents and instruction fields only.

In addition, the ARM architecture provides:

• Instructions that combine a shift with an arithmetic or logical operation
• Auto-increment and auto-decrement addressing modes to optimize program loops
• Load and Store Multiple instructions to maximize data throughput
• Conditional execution of almost all instructions to maximize execution throughput.

These enhancements to a basic RISC architecture enable ARM processors to achieve a good balance of high performance, small code size, low power consumption, and small silicon area.
The ARM Instruction Architecture is constantly improving to meet the increasing demands of leading edge applications developers, while retaining the backwards compatibility necessary to protect investment in software development.
ARM uses the Universal Assembly Language to provide a canonical form for all ARM and Thumb instructions.  This allows the user to write assembly code which can be assembled for either instruction set.