Instruction Set Architectures

The ARM processor architecture provides support for the 32-bit ARM and 16-bit Thumb^® Instruction Set Architectures (ISAs) along with architecture extensions to provide support for Java acceleration (Jazelle®), security (TrustZone®), SIMD, and NEON™ technologies.The ARM architecture supports implementations across a wide range of performance points. It is established as the dominant architecture in many market segments. The architectural simplicity of ARM processors leads to very small implementations, and small implementations mean devices can have very low power consumption. Implementation size, performance, and very low power consumption are key attributes of the ARM architecture.
The ARM architecture is a Reduced Instruction Set Computer (RISC) architecture, as it incorporates these typical RISC architecture features:

• Large uniform register file
• Load/store architecture, where data-processing operations only operate on register contents, not directly on memory contents
• Simple addressing modes, with all load/store addresses being determined from register contents and instruction fields only.

In addition, the ARM architecture provides:

• Instructions that combine a shift with an arithmetic or logical operation
• Auto-increment and auto-decrement addressing modes to optimize program loops
• Load and Store Multiple instructions to maximize data throughput
• Conditional execution of almost all instructions to maximize execution throughput.

These enhancements to a basic RISC architecture enable ARM processors to achieve a good balance of high performance, small code size, low power consumption, and small silicon area.
The ARM Instruction Architecture is constantly improving to meet the increasing demands of leading edge applications developers, while retaining the backwards compatibility necessary to protect investment in software development.
ARM uses the Universal Assembly Language to provide a canonical form for all ARM and Thumb instructions.  This allows the user to write assembly code which can be assembled for either instruction set.