0 ARM

The ARM 32-bit instruction set is the base 32-bit ISA used in the ARMv4T, ARMv5TEJ and ARMv6 architectures.  In these architectures it is used in applications requiring high performance, or for handling hardware exceptions such as interrupts and processor start-up.

The ARM 32-bit ISA is also supported in the Cortex™-A and Cortex-R profiles of the Cortex architecture for performance critical applications, and for legacy code.  Most of its functionality is subsumed into the Thumb-2 instruction set, which also benefits from improved code density.

ARM instructions are 32-bits wide, and are aligned on 4-byte boundaries.

All ARM instructions can also be "conditionalised" to only execute when previous instructions have set a particular condition code. This means that instructions only have their normal effect on the programmers’ model operation, memory and coprocessors if the N, Z, C and V flags in the Application Program Status Register satisfy a condition specified in the instruction. If the flags do not satisfy this condition, the instruction acts as a NOP, that is, execution advances to the next instruction as normal, including any relevant checks for exceptions being taken, but has no other effect.  This conditionalisation of instructions allows small sections of if- and while-statements to be encoded without the use of branch instructions.

The condition codes are:

Condition Code	Meaning
N	Negative condition code, set to 1 if  result is negative
Z	Zero condition code, set to 1 if the result of the instruction is 0
C	Carry condition code, set to 1 if the instruction results in a carry condition
V	Overflow condition code, set to 1 if the instruction results in an overflow condition.

0 Instruction Set Architectures

The ARM processor architecture provides support for the 32-bit ARM and 16-bit Thumb^® Instruction Set Architectures (ISAs) along with architecture extensions to provide support for Java acceleration (Jazelle®), security (TrustZone®), SIMD, and NEON™ technologies.The ARM architecture supports implementations across a wide range of performance points. It is established as the dominant architecture in many market segments. The architectural simplicity of ARM processors leads to very small implementations, and small implementations mean devices can have very low power consumption. Implementation size, performance, and very low power consumption are key attributes of the ARM architecture.
The ARM architecture is a Reduced Instruction Set Computer (RISC) architecture, as it incorporates these typical RISC architecture features:

• Large uniform register file
• Load/store architecture, where data-processing operations only operate on register contents, not directly on memory contents
• Simple addressing modes, with all load/store addresses being determined from register contents and instruction fields only.

In addition, the ARM architecture provides:

• Instructions that combine a shift with an arithmetic or logical operation
• Auto-increment and auto-decrement addressing modes to optimize program loops
• Load and Store Multiple instructions to maximize data throughput
• Conditional execution of almost all instructions to maximize execution throughput.

These enhancements to a basic RISC architecture enable ARM processors to achieve a good balance of high performance, small code size, low power consumption, and small silicon area.
The ARM Instruction Architecture is constantly improving to meet the increasing demands of leading edge applications developers, while retaining the backwards compatibility necessary to protect investment in software development.
ARM uses the Universal Assembly Language to provide a canonical form for all ARM and Thumb instructions.  This allows the user to write assembly code which can be assembled for either instruction set.